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TK75020
ZVS RESONANT CONTROLLER FEATURES
s Optimized for Off-Line and Battery Powered Operation s Internal Zero-Voltage Detector s Soft-Start s Pulse-by-Pulse Current Limit s Overdissipation Protection with Soft-Start s Overvoltage Protection with Soft-Start s Low-Current Standby mode s Programmable On/Off Timing s Enable Control
APPLICATIONS
s s s s Cold Cathode Fluorescent Lamps Resonant Power Supplies Power Supplies for Notebook Computers Power Supplies for Personal Electronics
DESCRIPTION
The TK75020 is a low-cost, high-performance Zero-Voltage Switching (ZVS) controller IC. The primary applications are in inverters for Cold Cathode Fluorescent Lamps (CCFL) and in ZVS quasi-resonant or multi-resonant converters. The combination of a unique (patent-pending) control concept and a ZVS resonant inverter generates low-distortion sine wave for the fluorescent lamp, leading to extended lamp life and high luminous efficiency. The IC features all necessary circuits of a controller for such applications, including externally adjustable timing parameters (frequency, Ton(min), Toff(max)), current limit, Soft-Start, enable, error amplifier, and a trimmed reference. The same reference is used for undervoltage protection and other critical internal biases. Supply current in the "off" mode is kept at a minimum level (2 A typical). Special care has been taken to avoid undesirable turn-on of the external power MOSFET when sufficient supply voltage is not available, or when the device is held in the off mode. Even with no Vcc applied, the drive pin of the IC will sink in excess of 20 mA while maintaining the voltage below 1 V to prevent that leakage currents turn on the power MOSFET. An internal zero-voltage detector monitors the voltage across the MOSFET and ensures that the turn-on will only take place under zero-voltage conditions. A unique overdissipation protection prevents the overheating of the power MOSFET in case the zero-voltage switching is lost. The TK75020 is available in a 14-lead surface mount package.
TK75020
ORDERING INFORMATION
DRV GND
750 20
VCC Vref CL ZVD EAOUT EAINV ODP
TK75020
Tape/Reel Code
OVP EN CT TOFF(MAX) TON/SS
TAPE/REEL CODE
TL: Tape Left
January 1999 TOKO, Inc.
Page 1
TK75020
ABSOLUTE MAXIMUM RATINGS
All Pins Except TON / SS, TOFF(MAX), VREF, CT, ODP and EN (Low Impedance Source) ................... 16 V TON / SS, TOFF(MAX), ref, CT, ODP Pins .......................... 6 V EN Pin ...................................................................... 16 V Power Dissipation (Note 1) ................................ 500 mW Maximum Current (VCC and ZVD Pins) .................. 20 mA Storage Temperature Range ................... -55 to +150 C Operating Temperature Range ...................-20 to +85 C Junction Temperature .......................................... 150 C Lead Soldering Temperature (10 s) ..................... 235 C
TK75020 ELECTRICAL CHARACTERISTICS
Test conditions: VCC = 12 V, VEN = 2.4 V, CT = 360 pF, ITON / SS = ITOFF(MAX) = 50 A, DRV is Open, TA = Full Operating Temperature Range, Typical numbers apply at TA = 25 C, unless otherwise specified. SYMBOL ICC(OFF) ICC(OFF,H) ICC(UVLO) ICC(ON) PARAMETER Supply Current OFF Supply Current OFF, HIGH Supply Current, UVLO Mode Supply Current ON TEST CONDITIONS VEN = 0 V VEN = 0 V, VCC = 16 V VCC = 5 V VCC = 6 V 6 V < VCC < 16 V Supply Current ON, DRV UVLO High Threshold UVLO Low Threshold UVLO Hysteresis VCC = 6 V, CDRV = 1 nF 6 V < VCC < 16 V 5.2 5.0 80 5.6 5.3 5.6 700 4.7 MIN TYP 2 MAX 100 2 1000 6 8 8 10 6.0 5.6 500 UNITS A mA A mA mA mA mA V V mV
ICC(ON,DRV) VCC(ON) VCC(OFF) VCC(HYST)
ON/OFF SECTION (EN PIN) VEN IEN Threshold Voltage Input Current 6 V < VCC < 16 V VEN = 2.4 V VEN = 0 V, (Note 2) -100 0.4 4 2.4 V A nA
REFERENCE SECTION (VREF PIN) Vref Reference Output Voltage Iref = 0 mA TA = 25 C TA = Full Range 3.8 3.7 4.0 4.0 4.0 15 -12 4.2 4.3 V V mV mV mA
|Vref(LOAD)| Load Regulation |Vref(LINE)| Iref(SC) Line Regulation Short Circuit Current
-1 mA < Iref < 0 mA 6 V < VCC < 16 V Vref = 0 V
Note 1: Power Dissipation is 500 mW when mounted as recommended. Derate at 4 mW/C for operation above 25C. Note 2: Guaranteed by design.
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January 1999 TOKO, Inc.
TK75020
TK75020 ELECTRICAL CHARACTERISTICS (CONT.)
Test conditions: VCC = 12 V, VEN = 2.4 V, CT = 360 pF, ITON / SS = ITOFF(MAX) = 50 A, DRV is Open, TA = Full Operating Temperature Range, Typical numbers apply at TA = 25 C, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
DRIVE SECTION (DRV PIN) VDRV(HIGH) Output High Voltage IDRV = -20 mA IDRV = -100 mA IDRV = 20 mA VDRV(LOW) Output Low Voltage IDRV = 200 mA IDRV = 20 mA, VCC = 0 V or VEN = 0 V IDRV(SRC,PK) IDRV(SINK,PK) tRISE tFALL Peak Source Current Peak Sink Current Rise Time Fall Time CDRV = 10 nF CDRV = 10 nF CDRV = 1 nF CDRV = 1 nF 9.0 10.0 9.8 0.3 1.8 0.9 500 700 70 25 120 75 0.6 2.5 1. 3 V V V V V mA mA ns ns
ERROR AMPLIFIER SECTION (EAINV AND EAOUT PINS) VEA(ref) IEA(INV) Equivalent Internal Reference Voltage Bias Current IEA(OUT) = -1 mA, VINV = 1.5 V 15 k From EAOUT to TON / SS 15 k From EAOUT to TON / SS, (Note 2) 6 V VCC 16 V 1.19 1.26 0.10 0.25 70 2 65 1.30 V A V dB MHz dB
VEA(OUT, LOW) Output Voltage LOW AOL GBW PSSR Open Loop Gain Gain-Bandwidth Product Power Supply Rejection Ratio
CURRENT LIMIT SECTION (CL PIN) ICL VCL(TH) tCL(DRV) Bias Current Threshold Voltage Delay to DRV VCL Steps From 0 to 400 mV VCL = 0 V 180 -0.2 210 150 240 A mV ns
ON-TIME SETTING AND SOFT-START SECTION (TON / SS PIN) ITON / SS (SC) VTON / SS VSS(TH) VDCH(TH) Short Circuit Current Pin Voltage Soft-Start Threshold ODP Discharge Threshold VTON / SS = 0 V ITON / SS = 0 mA 1.8 0.40 1.0 -2.5 2.0 0.65 1.4 2. 2 0.90 1. 9 mA V V V
January 1999 TOKO, Inc.
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TK75020
TK75020 ELECTRICAL CHARACTERISTICS (CONT.)
Test conditions: VCC = 12 V, VEN = 2.4 V, CT = 360 pF, ITON / SS = ITOFF(MAX) = 50 A, DRV is Open, TA = Full Operating Temperature Range, Typical numbers apply at TA = 25 C, unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
MAXIMUM OFF-TIME SETTING SECTION (TOFF(MAX) PIN) IT(OFF, MAX) VT(OFF, MAX) Short Circuit Current Pin Voltage VT(OFF, MAX) = 0 V IT(OFF, MAX) = 0 mA 1.8 2.5 2.0 2.2 mA V
TIMING SECTION (CT PIN) VCT(LOW) VCT(HIGH) f CTRTON CTRTOFF(MAX) Low Threshold Voltage High Threshold Voltage Oscillator Frequency Current Transfer Ratio to CT Pin, On-time Setting Current Transfer Ratio to CT Pin, Max Off-time Setting VCT = 4 V VCT = 0 V 0.9 2.7 115 -6.2 4.75 1.0 3.0 140 -5.5 5.25 1.1 3.3 165 -4.8 5.75 V V kHz
ZERO VOLTAGE DETECTOR SECTION (ZVD PIN) VZVD(TH) IZVD tZVD(DRV) Detector Low Threshold Input Current Delay to DRV TA = 25 C VZVD = 2 V VZVD Steps From 5 to 0 V, CDRV = 1 nF 1.8 -50 170 2.0 2.2 0 300 V A ns
OVERDISSIPATION DETECTOR SECTION (ODP PIN) VODP(TH) IODP(AVG) Detection Threshold Volage Average Current f = 100 kHz, TOVERLAP = 200 ns 0.45 0.70 0.6 0.95 V A
OVERVOLTAGE DETECTOR SECTION (OVP PIN) VOVP(TH) tOVP(D) Detection Threshold Volage Dealy to DRV 3.6 4.0 350 4.3 800 V ns
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January 1999 TOKO, Inc.
TK75020
BLOCK DIAGRAM
50 A ZVS DRIVE ZVD CMP
VCC D1 ZVD 2.5/2.7 V
TIMER REF +2 V Q11 Q9 Q10 VREF - VB R1 TOFF(MAX) 1K CT REF A1 Q1
1.5 V CMP4 G1
CMP3 3V
S DRV LATCH
G2 Q S Q R G3
B1 VCC DRIVE DRV EN3
1V
CMP2
R EN3
Q3
Q4
Q16 Q6 Q7 Q8 STAND-BY GATE DISCHARGE CL CMP CURRENT LIMITER CL S 0.21 V HIGH: RAMP DOWN
R2 TON/SS EAOUT 1.25 V EAINV 1K
A2
Q2
Q5
ERROR AMP R
Q
CL LATCH Q13 VBE SOFT START CMP ODP LATCH 2 VBE ODP DISCHARGE CMP Q15 Q17 REF Q R S G4 OVP Q14 G5 ODP CUR SRC ODP EN4 REF
Q12
OVERDISSIPATION VOLTAGE PROTECTION VCC VCC EN0 B0 EN START-UP BIAS VREF BANDGAP REF REF CMP HIGH: DRV ENABLED BIAS EN VCC OUT +4 V REF BUFFER EN1 EN2 B2 BUFFERED BIAS B1 5.8/5.3 V UVLO CMP EN1 VCC REF 3.0 V 2.0 V 1.5 V 1.25 V 1.0 V 0.21 V
GND
January 1999 TOKO, Inc.
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TK75020
PIN DESCRIPTION
SUPPLY VOLTAGE PIN (VCC) This pin is connected to the supply voltage. The IC begins normal operation when two conditions are met: 1) the VCC voltage exceeds 5.6 V and 2) the voltage of the enable pin exceeds 2.2 V. Operation ceases and the IC goes into a UVLO mode when the VCC voltage drops below 5.3 V. When the voltage at the enable pin becomes less than 0.4 V, the IC is turned off ("off" mode). In UVLO mode the current consumption is less than 300 A, in off mode it is further reduced to below 3 A. The operating voltage range is 6 V to 14 V. The tolerances of the start and stop voltages are 5.6 0.4 V and 5.3 0.3 V, respectively. During normal operation the total IC current consumption is less than 8 mA (no load, 100 kHz operation). When VCC is applied to the device with the enable pin pulled above 2.2 V ("on" mode), the following events will occur: First, a trimmed bandgap reference voltage will be generated as soon as VCC reaches about 4.8 V. This reference will be used to determine the UVLO thresholds. When VCC reaches the upper threshold of the undervoltage lockout comparator, that comparator enables the reference buffer. When the voltage at the output of the buffer, i.e. on the VREF pin, becomes higher than about 3.7 V, an enable signal is generated for the drive stage through gate G3. Normal operation may be interrupted at any time by pulling the enable pin below 0.4 V. When VCC is reduced below the lower threshold of the undervoltage lockout, the internal 4 V bias is disabled and the drive output is quickly turned off. The bandgap reference remains active as long as VCC is above 4.8 V. Special care has been taken to keep the drive output low even at a lower level of VCC in order to prevent unwanted turn-on of the external MOSFET. ENABLE (ON/OFF) PIN (EN) The enable pin is used to enable or disable the IC. The IC is guaranteed to turn on (i.e., to enter the "on" mode) when the pin voltage is above 2.2 V and is guaranteed to turn off when the pin voltage is below 0.4 V. If the On/Off feature is not needed, the pin can be connected directly to the supply voltage. The enable pin is internally equivalent to a 200 k resistor in series with two diodes. GROUND PIN (GND) This pin provides ground return connection for the IC. DRIVE PIN (DRV) This pin drives the external MOSFET. During standby, the DRV pin provides at least 20 mA current sinking capability with less than 1 V difference between the ground and the DRV pin. The internal circuitry connected to the DRV pin is designed to deliver a peak output voltage of 4 V above ground when the device operates at a minimum supply voltage of 6 V. An internal clamp circuit, however, ensures that the peak output voltage will never exceed 13 V. The DRV pin goes high only if the following five conditions are met simultaneously: 1) the drive (DRV) latch is set, 2) the overdissipation protection latch (ODP) is reset, 3) the current limit latch (CL) is reset, 4) the enable pin is pulled high, and 5) the output of the reference comparator is high, i.e., it detects that the voltage at the Vref pin is sufficiently high. CURRENT LIMIT PIN (CL) The CL pin is used for high-speed, cycle-by-cycle overload protection. When the voltage of the CL pin exceeds 0.2 V above ground, the current limit latch is set by the CL comparator and the output stage is forced low. At the same time, the timing capacitor is quickly discharged with transistor Q16. Note that a quick discharge is necessary in order to reduce the "on" time (and the duty ratio) without a significant increase in the effective "off" time. The current limit latch is reset when the output of the drive latch goes low, i.e., when the off time is over and the output of the CL comparator goes high. REFERENCE PIN (Vref) The bandgap reference, an internal 4 V source, is buffered by a reference buffer, whose output is connected to the Vref pin. The Vref pin voltage is enabled to develop when the upper threshold of the UVLO comparator is passed by VCC. TIMING CAPACITOR PIN (CT) The external timing capacitor is connected to the CT pin. The voltage across the timing capacitor oscillates between an upper level of 3 V and a lower level of 1 V. During the time the voltage of the timing capacitor is rising (due to the charging current set by the resistor between ground and the TOFF( MAX) pin), the drive latch is in the reset state and January 1999 TOKO, Inc.
Page 6
TK75020
PIN DESCRIPTION (CONT.)
the DRV pin is held low. The drive latch may be set either by the output of comparator CMP3 through the two-input OR gate G2 or by the ZVD comparator through G1 and G2. CMP3 detects if the timing voltage reached 3 V, the ZVD comparator detects if the voltage at the ZVD pin dropped below 2 V. Note that gate G1 allows setting the drive latch through the ZVD pin only when the voltage at the CT pin is higher than 1.5 V and the current limit latch is in the reset state. The reason for disabling the ZVD path at CT pin voltages lower than 1.5 V is to prevent an immediate turnon of the MOSFET after it was turned off. CMP4 is used to detect if the CT pin voltage is higher than 1.5 V. When the voltage of the timing capacitor is falling (due to the discharging current set by the external resistors between the output of the error amplifier and the TON/SS pin, as well as between the TON/SS pin and ground), the DRV pin is allowed to go high. The charge and discharge currents are enabled exclusively. ZERO VOLTAGE DETECTION PIN (ZVD) This pin is connected to the drain of the power MOSFET switch of the converter or inverter through a high value resistor or a diode. When the MOSFET is turned off, the drain voltage increases at first and then decreases, due to the resonant action in the loading network of the switch. When the drain voltage is above the supply voltage of the IC, the ZVD pin voltage is clamped to the supply voltage through the internal diode D1. As the drain voltage drops below the supply voltage, the voltage of the ZVD pin begins to follow it. When the ZVD pin voltage drops below 2 V, the output of the ZVD comparator goes high and sets the drive latch through gates G1 and G2. Unless there is a fault condition, the DRV pin goes high and turns on the MOSFET switch. By having the ZVD feature, the circuit automatically sets the optimum off time, essentially independently from the value of the resistor between the TOFF(MAX) pin and ground. ERROR AMPLIFIER PIN (EAOUT) The EAOUT pin is the output of the internal error amplifier. The output stage of the amplifier is an open-collector transistor. It is normally connected to the TON/SS pin via an external resistor. The non-inverting input of the error amplifier is internally tied to a trimmed 1.25 V reference. The error amplifier is short-circuit protected. ERROR AMPLIFIER INPUT PIN (EAINV) The EAINV pin (the inverting input of the error amplifier) serves for receiving either an external voltage-feedback or an external current-feedback signal. The compensating network of the feedback loop is usually connected between the EAINV and the EAOUT pins. TURN-ON TIMING / SOFT-START PIN (TON / SS) The on-time is inversely proportional to the current flowing in the resistor connected between this pin and the EAOUT pin. The TON/SS pin is also useful for providing Soft-Start at turn-on. Soft-Start can be achieved by connecting the series combination of a resistor and capacitor between the TON/SS pin and ground. When the normal operation of the IC is enabled (either because the VCC voltage exceeds the upper UVLO threshold or because the IC is turned on by the Enable pin), the Soft-Start capacitor, which was initially discharged, begins to charge up through the series resistor. The charging current adds to the current flowing in the ontime-setting resistor and sets a shorter on time. As the voltage builds up across the soft-start capacitor the charging current gradually decreases and the on time gradually increases. At normal operation a voltage-to-current converter formed by A2 and Q2 keeps the voltage of the TON/SS pin at 2 V. The current flowing through R2 and the external resistor connected to the TON/SS pin and ground is mirrored with Q3 and Q4 into a second mirror formed by Q5 and Q6. The diode-connected section of the second mirror is shorted with the transistor Q7 via Q8 when the current switch latch is reset. MAXIMUM TURNOFF TIMING PIN (TOFF(MAX)) An external resistor connected between this pin and ground sets the current that charges the timing capacitor. The maximum possible off time is inversely proportional to the value of that current. As discussed previously, when the off period is terminated by the zero-voltage detector, the actual off time becomes shorter than the value set by this resistor. At normal operation the voltage of the TOFF (MAX) pin is kept at 2 V with the help of a voltage-to-current converter formed by the amplifier A1 and transistor Q1. The current flowing through the off time setting resistor and R1 is
January 1999 TOKO, Inc.
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TK75020
PIN DESCRIPTION (CONT.)
mirrored by the transistors Q9 and Q10 and it charges the timing capacitor. The incoming mirror current is diverted from the mirror with transistor Q11 when the drive latch is set. OVERDISSIPATION PROTECTION PIN (ODP) The ODP pin is used to realize a protection against overdissipation of the power MOSFET due to the loss or absence of zero-voltage switching (ZVS). (ZVS can be lost if the load or the input voltage changes too much. ZVS is absent if the component values of the load network are far from optimal, or if the ZVD function is not implemented and the set off time is either too short or too long.) If ZVS is not present in a converter or inverter that was originally meant to operate with it, the MOSFET is turned on with a substantial voltage across it and the capacitor in parallel with it. Due to the periodic discharge of the parallel capacitor, a significant dissipation appears in the MOSFET. That dissipation is proportional to the switching frequency, the capacitance value, and the square of the voltage across the MOSFET at the instant of turn-on. The overdissipation protection works as follows: a current source is enabled when the MOSFET drain voltage is above the ZVD comparator threshold when the DRV pin voltage goes high. A short current pulse flows into the parallel combination of a resistor and capacitor connected between the ODP pin and ground and gradually begins to raise the pin voltage. When the pin voltage reaches about 0.7 V, the ODP latch is set via gate G4. The output signal of the ODP latch inhibits gate G3 and forces the drive output low. The output of the ODP latch also turns on transistors Q12-Q14. Q12 removes the 2 V reference signal from the noninverting input of amplifiers A1 and A2 . Q13 pulls down the EA OUT pin. The Soft-Start capacitor connected to the TON/ SS pin begins to discharge through the soft-start resistor (see application circuit) and the on-time setting resistor. When the voltage at the TON/SS pin drops below 2 VBE, the ODP discharge comparator turns on Q15, which pulls down the ODP pin voltage and discharges the capacitor connected to that pin. When the voltage at the TON/SS pin drops below a VBE, voltage the Soft-Start comparator resets the ODP latch. At that time the 2 V reference is enabled and a new Soft-Start cycle begins. The turnoff/soft restart cycle repeats until zero-voltage switching is reestablished. OVERVOLTAGE PROTECTION PIN (OVP) The OVP pin is used to monitor the voltage across a Page 8 January 1999 TOKO, Inc. winding of the transformer in the CCFL inverter. When the OVP comparator detects an overvoltage, it initiates a shutdown via G4 and a Soft-Start cycle begins.
TK75020
APPLICATION INFORMATION
VSW
TOFF TON
2.0 V 0
VSW iSW
0 0.2 V / RSENSE
i SW ZVD CMP
TOFF(MAX)
0 CL CLAMP 3.0 V 1.5 V 1.0 V 3.0 V CT 1.0 V CL LATCH Q DRV LATCH Q
CT
CMP4
DRV LATCH Q
NORMAL OPERATION
CYCLE-BY-CYCLE CURRENT LIMIT
VSW
2.0 V 0
VBE 0
i SW
ODP
0
CMP7
CMP3
CMP2
TOFF(MAX)
DRV ODP LATCH
2.0 V 1.5 V VBE
3.0 V
CT
1.0 V
TON / S.S
ZVD CMP DRV LATCH Q
OPERATION WITHOUT ZVD
OVERDISSIPATION PROTECTION
January 1999 TOKO, Inc.
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TK75020
APPLICATION INFORMATION (CONT.)
J1 1 2 3
VIN 6 TO 16 V
F1 1A
C4 22 16 V ODP VCC
L1 270 8RHB C6 47 n T1 (Note 2)
C1 100 n R5 18 k
INV EAOUT
GND
D1 1N4148
L2 82 8RHB n1= 19 C10 10 n R14 1k n2= 1520
J2 1 1 2 CCFL 220-250 mm
ZVD Q1 2SK1475 DRV R6 47 k
2
TON/SS R2 1k R3 22 k C2 10 F Q2 (Note 1) C3 680 p EN CT TOFF
R1 68 k
CL
D2 1N4148 Vref C5 100 n R9 470 k R13 10 k R11 68 k C9 100 n
OVP R10 100 k R12 3.3 k
Gen. Note: Q2 is not required if Q1 is an avalanche rated FET Gen. Note: Part #CTX01-13154 (Call Toko Technical Support (719) 528-2200).
LAPTOP DISPLAY BACKLIGHTING EXAMPLE
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January 1999 TOKO, Inc.
TK75020
PACKAGE OUTLINE
Marking Information
Marking 75020
SOP-14
0.76
TK75020
14
8
1.27
e
1.27
3.9
Recommended Mount Pad
1
7
8.65
0.5
1.45
+ 0.3
1.64
0 ~10
0.42
0.12 l
0.1
0.25 max
e 1.27
+ 0.3
6.07
Dimensions are shown in millimeters Tolerance: x.x = 0.2 mm (unless otherwise specified)
Toko America, Inc. Headquarters 1250 Feehanville Drive, Mount Prospect, Illinois 60056 Tel: (847) 297-0070 Fax: (847) 699-7864
TOKO AMERICA REGIONAL OFFICES
Midwest Regional Office Toko America, Inc. 1250 Feehanville Drive Mount Prospect, IL 60056 Tel: (847) 297-0070 Fax: (847) 699-7864 Western Regional Office Toko America, Inc. 2480 North First Street , Suite 260 San Jose, CA 95131 Tel: (408) 432-8281 Fax: (408) 943-9790 Eastern Regional Office Toko America, Inc. 107 Mill Plain Road Danbury, CT 06811 Tel: (203) 748-6871 Fax: (203) 797-1223 Semiconductor Technical Support Toko Design Center 4755 Forge Road Colorado Springs, CO 80907 Tel: (719) 528-2200 Fax: (719) 528-2375
Visit our Internet site at http://www.tokoam.com
The information furnished by TOKO, Inc. is believed to be accurate and reliable. However, TOKO reserves the right to make changes or improvements in the design, specification or manufacture of its products without further notice. TOKO does not assume any liability arising from the application or use of any product or circuit described herein, nor for any infringements of patents or other rights of third parties which may result from the use of its products. No license is granted by implication or otherwise under any patent or patent rights of TOKO, Inc.
January 1999 TOKO, Inc.
(c) 1999 Toko, Inc. All Rights Reserved IC-122-TK75020 0798O0.0K
0.2
e1
5.4
Page 11
Printed in the USA

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